Keynotes
Polar Opposites: Next Generation Languages and Architectures
Kathryn S McKinley, University of Texas at Austin
Future hardware technology is on a collision course with modern
programming languages. Adoption of programming languages is rare and
slow, but programmers are now embracing high-level object-oriented
languages such as Java and C# due to their software engineering
benefits which include (1) fast development through code reuse and
garbage collection; (2) ease of maintenance through encapsulation and
object-orientation; (3) reduced errors through type safety, pointer
disciplines, and garbage collection; and (4) portability. These
programs use small methods, dynamic class binding, heavy memory
allocation, short-lived objects, and pointer data structures, and thus
obscure parallelism, locality, and control flow, in direct conflict
with hardware trends.
At the other end of technology, the limits of silicon are on the verge
of creating a dramatic shift in computer architectures. Due to wire
scaling and clock rates, processors will soon access only a fraction
of the chip in a single cycle. This limited reach will (1) necessitate
partitioning structures such as caches and predictors, (2) make the
memory hierarchy slower and more complex, and (3) require the
processor to exploit fine grain instruction level parallelism (ILP)
for performance. Radical hardware solutions promise to exacerbate
current performance issues for modern languages.
We outline our total system approach to avoiding this collision. We
present the TRIPS architectural solution to technology limits, and
discuss its implications for modern languages, their compilers, and
memory management. We include some of our recent results on
cooperative caching, the influence of garbage collection on program
performance, and online mechanisms for improving program locality.