MSP 2004, Memory Systems Performance June 8, 2004
On-line Proceedings
* made temporarily available before the inclusion into the ACM digital library

Keynote: Jack Davidson

Memory System Performance and the Innovator's Delimma, page 1

Session I Transformation

Instruction Combining For Coalescing Memory Accesses Using Global Code Motion, Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatani (IBM Tokyo Research Laboratory), pages 2-11

Automatic Blocking Of QR and LU Factorizations for Locality, Qing Yi (Lawrence Livermore National Laboratory), Ken Kennedy (Rice University), Haihang You, Keith Symour, Jack Dongarra (University of Tennessee), pages 12-22

Metrics and Models for Reordering Transformations Michelle Strout, Paul Hovland (Argonne National Laboratory and University of Chicago), pages 23-34

1:30-2:30 Keynote: Kathryn McKinley

Polar Opposites: Next Generation Languages and Architectures, page 35

2:30-3:40 Session II Memory Systems

Improving Trace Cache Hit Rates Using the Sliding Window Fill Mechanism and Fill Select Table, Muhammad Shaaban, Edward Mulrane (Rochester Institute of Technology), pages 36-41

An Empirical Performance Analysis of Commodity Memories in Commodity Servers, Darren Kerbyson, Mike Lang (Los Alamos National Laboratory),  Gene Patino, Hossein Amidi (Smart Modular Technologies Inc), pages 42-50

4:10-5:20 Session III Analysis and Language Support

Programmer Specified Pointer Independence, David Koes, Mihai Budiu, Girish Venkataramani, Seth Goldstein (Carnegie Mellon University), pages 51-59

Reuse-distance-based Miss-rate Prediction on a Per Instruction Basis, Changpeng Fang, Steve Carr, Soner Onder, Zhenlin Wang (Michigan Technological University), pages 60-69