Building Programs with make

• Why do we need a way to build programs?
  • Programs are composed of many parts.
  • It is difficult to remember the order of operations to build a complicated program.
  • We want to make sure the latest versions of source code are compiled.
  • We want to do as little work as possible to get a consistent program build.
  
  
• How does make help solve these problems?
  • All instructions for putting a program together are contained in one file.
  • Dependencies are specified between files
  • Work is done only when a target file is older than one of the files listed in its dependency list

Defining a make file

• make will look in the current directory for a file named makefile or Makefile.
  
  
• makefile is composed of three sections:

  Macro definitions

  define macro constant used in the make file

  Suffix or generic rules

  specify general rules for building components of a program

  Dependencies

  specify targets, the files they are dependent on and how to build a target from the files it is dependent on
  

  First two sections are optional.

Dependencies

• Dependencies are based on a target and several files on which the target is dependent.
  
  
• If one of the dependent files is newer than the target file then a set of rules (commands) will be executed to bring the target up to date.

           target : dependencies
                rules
    
           StringClass.o : StringClass.cc StringClass.h
                g++ -Wall -c StringClass.cc
    

  All rules must be one TAB in from left margin. There can be multiple lines of rules for each dependency.
  
  
• make will create a tree of dependencies to ensure that all targets are up to date

           StringTest : StringTest.o StringClass.o
                g++ -o StringTest StringTest.o StringClass.o
    
           StringTest.o : StringTest.cc StringClass.h
                g++ -Wall -c StringTest.cc
    
           StringClass.o : StringClass.cc StringClass.h
                g++ -Wall -c StringClass.cc
    

  make defaults to building the first target specified in the make file. It looks at each of the dependencies and ensures that they are up to date performing the defined steps if they are not.
  
  
• Suffix rules, based on file extensions, can define generic dependencies

           .cc.o :
                g++ -Wall -c $<
    

  This defines the generic build a .o from .c rule. It uses one of make's builtin macros described below.
  Note the reverse of the target/dependency extension.
  
  
• make has several builtin macros
  1. $< - the current dependcy file
  2. $@ - the current target file
  3. $* - the base name of the current target
  4. $? - all dependencies that are newer than the target
  
  
• Macros allow you to define constants used in the make file.

           name = definition
    
           C++ = g++
           C++OPTS = -Wall
           LDOPTS = -L/u/csc173/ca1cs173/lib
    
           STRINGTESTOBJS = StringTest.o StringClass.o
    
           .cc.o :
                $(C++) $(C++OPTS) -c $<
    
           StringTest : $(STRINGTESTOBJS)
                $(C++) -o $@ $(STRINGTESTOBJS) $(LDOPTS)
    

  
  
• Pattern matching rules are a little more general than suffix rules. % is used as a wildcard character. The rule will be used if a target line matches the pattern.

           C++ = g++
           C++OPTS = -Wall
           LDOPTS = -L/u/csc173/ca1cs173/lib
    
           STRINGTESTOBJS = StringTest.o StringClass.o
    
           %.o : %.cc
                $(C++) $(C++OPTS) -c $<
    
           StringTest : $(STRINGTESTOBJS)
                $(C++) -o $@ $(STRINGTESTOBJS) $(LDOPTS)
    
           StringTest.o : StringTest.cc StringClass.h
    
           StringClass.o : StringClass.cc StringClass.h