Coherence Algorithms for SHared MEmory aRchitectures

The CASHMERe Project

Overview

CASHMERe stands for "Coherence Algorithms for SHared MEmory aRchitectures" and is an ongoing effort to provide efficient, scalable, shared memory with minimal hardware support. It is well accepted today that commercial workstations offer the best price/performance ratio and that shared memory provides the most desirable programming paradigm for parallel computing. Unfortunately shared memory emulations on networks of workstations provide acceptable performance for only a limited class of applications. CASHMERe attempts to bridge the performance gap between shared memory emulations on networks of workstations and tightly-coupled cache-coherent multiprocessors while using minimal hardware support.

In the context of CASHMERe, early simulation results indicate that NCC-NUMA (Non Cache Coherent Non Uniform Memory Access) machines can greatly improve the performance of DSM systems, and approach that of fully hardware coherent multiprocessors. The basic property of NCC-NUMA systems is the ability to access remote memory directly; such a capability is offered by a variety of network interfaces including DEC's Memory Channel, HP's Hamlyn, the VIA standard, the Scheduled Transfer standard, and the Princeton Shrimp. Given current technology the additional hardware cost of NCC-NUMA systems over pure message passing systems is minimal. Based on this fact and our performance results we believe that NCC-NUMA machines lie near the knee of the price-performance curve.

The department of Computer Science at the University of Rochester has built a 32 processor Cashmere prototype. Significant part of the funding comes in the form of an equipment grant from Digital Equipment Corporation. The prototype consists of eight 4-processor DEC 4100 4/600 multiprocessors with 2GB of memory each, connected by a Memory Channel network. The Memory Channel plugs into any PCI bus. It provides a memory-mapped network interface with which processors can read and write remote locations without kernel intervention or inter-processor interrupts. End-to-end bandwidth is currently about 70MB/sec; remote write latency is about 3.5us; cross-sectional bandwidth is approximately 500MB/sec. Cashmere augments the functionality of the Memory Channel by providing cache coherence in software. As Cashmere has matured, more and more effort is being directed toward the follow-on InterAct project.

CASHMERe People

The people behind CASHMERe are
Faculty
Alumni

Overview presentation (PDF format), March 1999

Other Presentations

Annual reports to the NSF Experimental Software Systems Program

Grant CCR-9705594, 6-1-1997 to 5-31-2001.

CASHMERe papers

Patent

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Last Change: 13 October 2006 / scott@cs.rochester.edu