We have shown that adopting a lazy consistency protocol on hardware-coherent multiprocessors can provide substantial performance gains over the eager alternative on a variety of applications. For systems with programmable protocol processors, the lazy protocol requires only minimal additional hardware cost (basically storage space) with respect to eager release consistency. We have introduced two variants of lazy release consistency and have shown that on hardware-based systems, delaying coherence transactions helps only up to a point. Delaying invalidations until a synchronization acquire point is almost always beneficial, but delaying the posting of write notices until a synchronization release point tends to move background coherence operations into the critical path of the application, resulting in unacceptable synchronization overhead.
We have also conducted experiments in an attempt to evaluate the importance of lazy release consistency on future architectures. We find that as miss latencies and cache line sizes increase, the performance gap between lazy and eager release consistency increases as well. We are currently investigating the interaction of lazy hardware consistency with software techniques that reduce the amount of false sharing in applications. As program locality increases the performance advantage of lazy protocols will decrease, as a direct result of the decrease in coherence transactions required. Our results indicate, however, that lazy protocols can improve application performance even in the absence of false sharing, e.g. by replacing 3-hop transactions with 2-hop transactions, as in gauss, or by eliminating write-buffer stalls due to write-after-read operations, as in barnes-hut. Moreover, since most parallel applications favor small cache lines while the current architectural trend is towards longer lines, we believe that lazy consistency will provide significant performance gains over eager release consistency for the foreseeable future.