CoSyn
Communication and Synchronization Mechanisms for Emerging Multi-Core Processors

This work has been supported in part by NSF grants CCF-0702505, CNS-0411127, CNS-0615139, and CNS-0509270; an IBM Faculty Partnership Award; NIH grants 5 R21 GM079259-02 and 1 R21 HG004648-01; and equipment support from Sun Microsystems Laboratories. Most of our simulation models are built on top of the Wisconsin GEMS models. We employ Virtutech Simics to faithfully emulate the functionality of our target systems.

Overview

As a result of increasing chip density and power limitations, explicit hardware parallelism has begun to dominate the computing spectrum, with multicore chips replacing uniprocessors throughout the desktop and laptop markets. If these chips are to be used effectively, new programming models must ease the task of writing multithreaded code. These models must in turn be supported by architectural mechanisms that minimize the cost of data communication and synchronization. This project addresses the challenge of mainstream parallelism at both the hardware and software level.

One key idea is to identify common time-critical operations, across a variety of applications and programming models, that might be accelerated or simplified by new architectural mechanisms, and then to design those mechanisms in as general a fashion as possible. By leaving policy to software whenever possible, this strategy aims to maximize opportunities for adaptive and application-specific protocols that increase scalability. Candidate hardware mechanisms include alert-on-update, which leverages cache coherence for fast event-based communication; programmable data isolation, which allows a processor to hide local writes for speculation and transactions; and adaptive cooperative caching, which re-engineers the on-chip coherence protocol to accommodate different patterns of data sharing and to communicate values efficiently between cores.

Through better parallel programming models and efficient implementations, the project aims to continue the computing revolution over the course of the coming decade. By enabling the effective use of larger numbers of simpler cores, it also addresses the critical need to reduce energy consumption in mainstream processors.

People

Principal Investigator
Sandhya Dwarkadas
in collaboration with  Michael L. Scott
                          and  Michael C. Huang
Graduate Students
Alumni
M.S.
  • Nitin Bhardwaj (First Job: Intel, Oregon)
  • Rajeev Garg (First Job: Intel, Folsom)
Ph.D.

Papers

  • "SPATL: Honey, I Shrunk the Coherence Directory", H. Zhao, A. Shriraman, S. Dwarkadas, and V. Srinivasan, International Symposium on Parallel Architectures and Compilation Techniques (PACT), October 2011.

  • "POPS: Coherence Protocol Optimization for Both Private and Shared Data", H. Hossain, S. Dwarkadas, and M. Huang, International Symposium on Parallel Architectures and Compilation Techniques (PACT), October 2011.

  • "SPACE: Sharing Pattern-based Directory Coherence for Multicore Scalability", H. Zhao, A. Shriraman, and S. Dwarkadas, International Symposium on Parallel Architectures and Compilation Techniques (PACT), September 2010.

  • "Sentry: Light-Weight Auxiliary Memory Access Control", A. Shriraman and S. Dwarkadas, International Symposium on Computer Architecture (ISCA), June 2010.

  • "DDCache: Decoupled and Delegable Cache Data and Metadata", H. Hossain, S. Dwarkadas, and M. Huang, International Symposium on Parallel Architectures and Compilation Techniques (PACT), September 2009.

  • Refereeing Conflicts in Hardware Transactional Memory, A. Shriraman and S. Dwarkadas, International Conference on Supercomputing (ICS), June 2009.

  • Tapping into Parallelism with Transactional Memory, A. Shriraman, S. Dwarkadas, and M. L. Scott, ;login: (the USENIX Magazine), April 2009.

  • Improving Support for Locality and Fine-Grain Sharing in Chip Multiprocessors, H. Hossain, S. Dwarkadas, and M. C. Huang, International Symposium on Parallel Architectures and Compilation Techniques (PACT), October 2008.

  • Flexible Decoupled Transactional Memory Support, A. Shriraman, S. Dwarkadas, and M. L. Scott, International Symposium on Computer Architecture (ISCA), June 2008.

  • DIMM: Architectural Support for Data Isolation and Memory Monitoring, A. Shriraman, S. Dwarkadas, and M. L. Scott, poster presentation, 13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2008.

  • An Integrated Hardware-Software Approach to Flexible Transactional Memory, A. Shriraman, M. F. Spear, H. Hossain, V. J. Marathe, S. Dwarkadas, and M. L. Scott, 34th Intl. Symp. on Computer Architecture (ISCA), San Diego, CA, June 2007. Earlier but expanded version available as TR 910, Computer Science Dept., Univ. of Rochester, Dec. 2006.

  • Nonblocking Transactions Without Indirection Using Alert-on-Update, M. F. Spear, A. Shriraman, L. Dalessandro, S. Dwarkadas, and M. L. Scott, 19th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), San Diego, CA, June 2007.

  • Alert-on-Update: A Communication Aid for Shared Memory Multiprocessors (poster paper), M. F. Spear, A. Shriraman, H. Hossain, S. Dwarkadas, and M. L. Scott, Twelfth ACM Symp. on Principles and Practice of Parallel Programming (PPoPP), Mar. 2007.

  • Hardware Acceleration of Software Transactional Memory, A. Shriraman, V. J. Marathe, S. Dwarkadas, M. L. Scott, D. Eisenstat, C. Heriot, W. N. Scherer III, and M. F. Spear, Workshop on Languages, Compilers, and Hardware Support for Transactional Computing (TRANSACT), June 2006. In conjunction with PLDI'06. Earlier, extended version available as TR 887, Computer Science Department, University of Rochester, Dec. 2005, revised Mar. 2006.